Integrated circuits, including computer chips, are manufactured by building up layers of circuits on the front side of silicon wafers. An extremely high degree of wafer flatness and layer flatness is required during the manufacturing process. Chemical-mechanical planarization (CMP) is a process used during device manufacturing to flatten wafers and the layers built-up on wafers to the necessary degree of flatness.
Chemical-mechanical planarization is a process involving polishing of a wafer with a polishing pad combined with the chemical and physical action of a slurry pumped onto the pad. The wafer is held by a wafer carrier, with the backside of the wafer facing the wafer carrier and the front side of the wafer facing a polishing pad. The polishing pad is held on a platen, which is usually disposed beneath the wafer carrier. Both the wafer carrier and the platen are rotated so that the polishing pad polishes the front side of the wafer. A slurry of selected chemicals and abrasives is pumped onto the pad to affect the desired type and amount of polishing. (CMP is therefore achieved by a combination of chemical softener and physical downward force that removes material from the wafer or wafer layer.)
Using the CMP process, a thin layer of material is removed from the front side of the wafer or wafer layer. The layer may be a layer of oxide grown or deposited on the wafer or a layer of metal deposited on the wafer. The removal of the thin layer of material is accomplished so as to reduce surface variations on the wafer. Thus, the wafer and layers built-up on the wafer are very flat and/or uniform after the process is complete. Typically, more layers are added and the chemical mechanical planarization process repeated to build complete integrated circuit chips on the wafer surface.
A variety of wafer carrier configurations are used during CMP. One such wafer carrier configuration is the hard backed configuration. The hard backed configuration utilizes a rigid surface such as a piston or backing plate against the backside of the silicon wafer during CMP forcing the front surface of the silicon wafer to the surface of the polishing pad. Using this type of carrier may not conform the front wafer surface of the wafer to the surface of the polishing pad resulting in planarization non-uniformities. Such hard backed wafer carrier designs generally utilize a relatively high polishing pressure. These relatively high pressures effectively deform the wafer to match the surface conformation of the polishing pad. When wafer surface distortion occurs, the high spots are polished at the same time as the low spots giving some degree of uniformity but also resulting in poor planarization. Too much material from some areas of the wafer will be removed and too little material from other areas will also be removed. In addition to wafer distortion, the relatively high pressure also results in excessive material removal along the edges of the silicon wafer. When the amount of material removed is excessive, the entire wafer or portions of the wafer become unusable.
In other wafer carrier configurations, the wafer is pressed against the polishing pad using a membrane or other soft material. Use of a membrane carrier tends to avoid or limit distortion of the wafer. Lower polishing pressures may be employed, and conformity of the wafer front surface is achieved without distortion so that both some measure of global polishing uniformity and good planarization may be achieved. Better planarization uniformity is achieved at least in part because the polishing rate on similar features from die to die on the wafer is the same.
In our prior patents, Fuhriman, et al., Wafer Carrier with Pressurized Membrane and Retaining Ring Actuator, U.S. Pat. No. 7,238,083 (Apr. 25, 2006) and Spiegel, Independent Edge Control for CMP Carriers, U.S. Pat. No. 7,033,252 (Jun. 20, 2006) we disclose CMP systems which employ flexible membrane assemblies, and disclose inventive features which provide for enhanced control of the CMP process to limit the edge effect. The flexible membrane assemblies comprise a round pan-like assembly, constructed of a single piece of synthetic rubber or other pliable material. The membrane portion of the pan (the bottom) is held in place within the wafer carrier by its cylindrical side-wall and its flange which are trapped within other components of the wafer carrier. Along with the advances shown in our prior patents, this construction aids in the reduction of the edge effect which limits yield in CMP processes.